An EPROM is a read only memory device in which the stored data may be erased and new data written in its stead. A widely used type of EPROM is a floating gate field effect transistor type. See Sze, Physics of Semiconductor Devices, Section 8.61 (1981).
A partial schematic diagram of an EPROM using floating gate field effect transistors is shown in FIG. 1. Memory cells 26-1-1 through 26-2-4 are floating gate field effect transistors. Row decoder 28 provides output signals on row lines 24-1 and 24-2 in response to signals provided on row address input leads 21 and from read/write indicator 23. Column decoder 29 provides and receives signals on column lines 25-1 through 25-5 in response to signals provided on column address input leads 22 and from read/write indicator 23. A memory output signal is provided on output lead 27.
A data bit stored in, for example, memory cell 26-1-1 is read by providing a high voltage output signal on row line 24-1 and providing a low voltage output signal on all other row lines. Column decoder 29 then senses, via column lines 25-1 and 25-2, the impedance of memory cell 26-1-1. If the floating gate of memory cell 26-1-1 contains excess electrons, the negative charge of these excess electrons raises the threshold voltage of memory cell 26-1-1 so that the voltage provided on row line 24-1 is insufficient to cause the channel of memory cell 26-1-1 to conduct. Therefore, column decoder 29 detects a high impedance and provides an appropriate signal on output lead 27. If there are no excess electrons stored on the floating gate on memory cell 26-1-1 then the voltage supplied on row line 24-1 is sufficient to cause memory cell 26-1-1 to conduct. Therefore, column decoder 29 detects a low impedance and provides the appropriate signal on output lead 27.
EPROM 20 is thus programmed by negatively charging the floating gate of selective memory cells. This is accomplished by injecting hot electrons through the insulating layer beneath the floating gate from the substrate of the memory cell.
A problem involved with the fabrication of EPROMs using the techniques in the prior art (see for example McElroy, U.S. Pat. No. 4,151,021, entitled "Method of Making A High Density Floating Gate Electrically Programmable ROM", issued Apr. 24, 1979) occurs during the formation of thick field regions 29 of FIG. 4b of McElroy. These regions are formed in the prior art by thermal oxidation. Thermal oxidation consumes silicon from the substrate laterally as well as vertically. Thus a buffer region must be allowed in the patterning of the oxidation mask for thick oxide regions to provide for this lateral movement of the oxidized region. This buffer region increases the substrate surface area required to fabricate an EPROM using prior art techniques.
Planar technology provides for a small memory cell, which is more reliable. Despite the superior qualities of the planar FAMOS transistor, a programming voltage of 12.5 volts is still necessary for reliable programming. In order to reduce the magnitude of the electric fields created during programming, it is desirable that the programming voltage be reduced.
Therefore, a need has arisen for a planar and non-planar FAMOS technology for use in EPROMs, EEPROMs, EPALs, and other devices using similar memory structures, in which the programming voltage is reduced, and the reliability of the devices increased.